Assembly Language

This web page examines program control instructions in assembly language. Specific examples of instructions from various processors are used to illustrate the general nature of assembly language.

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• table of contents for assembly language section
• program control
• condition codes
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program control

Program control instructions change or modify the flow of a program.

The most basic kind of program control is the unconditional branch or unconditional jump. Branch is usually an indication of a short change relative to the current program counter. Jump is usually an indication of a change in program counter that is not directly related to the current program counter (such as a jump to an absolute memory location or a jump using a dynamic or static table), and is often free of distance limits from the current program counter.

The pentultimate kind of program control is the conditional branch or conditional jump. This gives computers their ability to make decisions and implement both loops and algorithms beyond simple formulas.

Most computers have some kind of instructions for subroutine call and return from subroutines.

There are often instructions for saving and restoring part or all of the processor state before and after subroutine calls. Some kinds of subroutine or return instructions will include some kinds of save and restore of the processor state.

Even if there are no explicit hardware instructions for subroutine calls and returns, subroutines can be implemented using jumps (saving the return address in a register or memory location for the return jump). Even if there is no hardware support for saving the processor state as a group, most (if not all) of the processor state can be saved and restored one item at a time.

NOP, or no operation, takes up the space of the smallest possible instruction and causes no change in the processor state other than an advancement of the program counter and any time related changes. It can be used to synchronize timing (at least crudely). It is often used during development cycles to temporarily or permanently wipe out a series of instructions without having to reassemble the surrounding code.

Stop or halt instructions bring the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset, or external action.

Reset instructions reset the processor. This may include any or all of: setting registers to an initial value, setting the program counter to a standard starting location (restarting the computer), clearing or setting interrupts, and sending a reset signal to external devices.

• BRA Branch; Motorola 680x0, Motorola 68300; short (16 bit) unconditional branch relative to the current program counter
• JMP Jump; Motorola 680x0, Motorola 68300; unconditional jump (any valid effective addressing mode other than data register)
• JMP Jump; Intel 80x86; unconditional jump (near [relative displacement from PC] or far; direct or indirect [based on contents of general purpose register, memory location, or indexed])
• JMP Jump; MIX; unconditional jump to location M; J-register loaded with the address of the instruction which would have been next if the jump had not been taken
• JSJ Jump, Save J-register; MIX; unconditional jump to location M; J-register unchanged
• Jcc Jump Conditionally; Intel 80x86; conditional jump (near [relative displacement from PC] or far; direct or indirect [based on contents of general purpose register, memory location, or indexed]) based on a tested condition: JA/JNBE, JAE/JNB, JB/JNAE, JBE/JNA, JC, JE/JZ, JNC, JNE/JNZ, JNP/JPO, JP/JPE, JG/JNLE, JGE/JNL, JL/JNGE, JLE/JNG, JNO, JNS, JO, JS
• Bcc Branch Conditionally; Motorola 680x0, Motorola 68300; short (16 bit) conditional branch relative to the current program counter based on a tested condition: BCC, BCS, BEQ, BGE, BGT, BHI, BLE, BLS, BLT, BMI, BNE, BPL, BVC, BVS
• JOV Jump on Overflow; MIX; conditional jump to location M if overflow toggle is on; if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken
• JNOV Jump on No Overflow; MIX; conditional jump to location M if overflow toggle is off; if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken
• Jcc Jump on Condition; MIX; conditional jump to location M based on comparison indicator; if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken; JL (less), JE (equal), JG (greater), JGE (greater-or-equal), JNE (unequal), JLE (less-or-equal)
• JAcc Jump on A-register; MIX; conditional jump to location M based on A-register (accumulator); if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken; JAN (negative), JAZ (zero), JAP (positive), JANN (nonnegative), JANZ (nonzero, JAMP (nonpositive)
• JXcc Jump on X-register; MIX; conditional jump to location M based on X-register (extension); if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken; JXN (negative), JXZ (zero), JXP (positive), JXNN (nonnegative), JXNZ (nonzero, JXMP (nonpositive)
• Jicc Jump on I-register; MIX; conditional jump to location M based on one of five I-registers (index); if jump occurs, J-register loaded with the address of the instruction which would have been next if the jump had not been taken; JiN (negative), JiZ (zero), JiP (positive), JiNN (nonnegative), JiNZ (nonzero, JiMP (nonpositive)
• DBcc Test Condition, Decrement, and Branch; Motorola 680x0, Motorola 68300; used to implement DO loops, WHILE loops, UNTIL loops, and similar constructs, starts by testing a designated condition, if the test is true then no additional action is taken and the program continues to the next instruction (exiting the loop), if the test is false then the designated data register is decremented, if the result is exactly -1 then the program continues to the next instruction (exiting the loop), otherwise the program makes a short (16 bit) branch (continueing the loop): DBCC, DBCS, DBEQ, DBF, DBGE, DBGT, DBHI, DBLE, DBLS, DBLT, DBMI, DBNE, DBPL, DBT, DBVC, DBVS
• LOOP Loop While ECX Not Zero; Intel 80x86; used to implement DO loops, decrements the ECX or CX (count) register and then tests to see if it is zero, if the ECX or CX register is zero then the program continues to the next instruction (exiting the loop), otherwise the program makes a byte branch to contine the loop; does not modify flags
• LOOPE Loop While Equal; Intel 80x86; used to implement DO loops, WHILE loops, UNTIL loops, and similar constructs, decrements the ECX or CX (count) register and then tests to see if it is zero, if the ECX or CX register is zero or the Zero Flag is clear (zero) then the program continues to the next instruction (to exit the loop), otherwise the program makes a byte branch (to continue the loop); equivalent to LOOPZ; does not modify flags
• LOOPNE Loop While Not Equal; Intel 80x86; used to implement DO loops, WHILE loops, UNTIL loops, and similar constructs, decrements the ECX or CX (count) register and then tests to see if it is zero, if the ECX or CX register is zero or the Zero Flag is set (one) then the program continues to the next instruction (to exit the loop), otherwise the program makes a byte branch (to continue the loop); equivalent to LOOPNZ; does not modify flags
• LOOPNZ Loop While Not Zero; Intel 80x86; used to implement DO loops, WHILE loops, UNTIL loops, and similar constructs, decrements the ECX or CX (count) register and then tests to see if it is zero, if the ECX or CX register is zero or the Zero Flag is set (one) then the program continues to the next instruction (to exit the loop), otherwise the program makes a byte branch (to continue the loop); equivalent to LOOPNE; does not modify flags
• LOOPZ Loop While Zero; Intel 80x86; used to implement DO loops, WHILE loops, UNTIL loops, and similar constructs, decrements the ECX or CX (count) register and then tests to see if it is zero, if the ECX or CX register is zero or the Zero Flag is clear (zero) then the program continues to the next instruction (to exit the loop), otherwise the program makes a byte branch (to continue the loop); equivalent to LOOPE; does not modify flags
• JCXZ Jump if Count Register Zero; Intel 80x86; conditional jump if CX (count register) is zero; used to prevent entering loop if the count register starts at zero; does not modify flags
• JECXZ Jump if Extended Count Register Zero; Intel 80x86; conditional jump if ECX (count register) is zero; used to prevent entering loop if the count register starts at zero; does not modify flags
• CASE Case; DEC VAX; the base operand is subtracted from the selector operand, creating an unsigned index, the index is compared to the limit operand and the case is skipped if it exceeds the limit, if within the limit then the index is used to compute the location into the displacement table and the displacement is used for an unconditional branch; and sets or clears flags; See DEC example
• Scc Set According to Condition; Motorola 680x0, Motorola 68300; tests a condition code, if the condition is true then sets a byte (8 bits) of a data register or memory location to TRUE (all ones), if the condition is false then sets a byte (8 bits) of a data register or memory location to FALSE (all zeros): SCC, SCS, SEQ, SF, SGE, SGT, SHI, SLE, SLS, SLT, SMI, SNE, SPL, ST, SVC, SVS
• SETcc Set Byte on Condition cc; Intel 80x86; tests a condition code, if the condition is true then sets a byte (8 bits) of a data register or memory location to TRUE (all ones), if the condition is false then sets a byte (8 bits) of a data register or memory location to FALSE (all zeros): SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ
• BSR Branch to Subroutine; Motorola 680x0, Motorola 68300; pushes the address of the next instruction following the subroutine call onto the system stack, decrements the system stack pointer, and changes program flow to a location (8, 16, or 32 bits) relative to the current program counter
• JSR Jump to Subroutine; Motorola 680x0, Motorola 68300; pushes the address of the next instruction following the subroutine call onto the system stack, decrements the system stack pointer, and changes program flow to the address specified (any valid effective addressing mode other than data register)
• CALL Call Procedure; Intel 80x86; pushes the address of the next instruction following the subroutine call onto the system stack, decrements the system stack pointer, and changes program flow to the address specified (near [relative displacement from PC] or far; direct or indirect [based on contents of general purpose register or memory location])
• RTS Return from Subroutine; Motorola 680x0, Motorola 68300; fetches the return address from the top of the system stack, increments the system stack pointer, and changes program flow to the return address
• RET Return From Procedure; Intel 80x86; fetches the return address from the top of the system stack, increments the system stack pointer, and changes program flow to the return address; optional immediate operand added to the new top-of-stack pointer, effectively removing any arguments that the calling program pushed on the stack before the execution of the corresponding CALL instruction; possible change to lesser privilege
• RTR Return and Restore Condition Codes; Motorola 680x0, Motorola 68300; transfers the value at the top of the system stack into the condition code register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer, and changes program flow to the return address
• IRET Return From Interrupt; Intel 80x86; transfers the value at the top of the system stack into the flags register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer, and changes program flow to the return address; optional immediate operand added to the new top-of-stack pointer, effectively removing any arguments that the calling program pushed on the stack before the execution of the corresponding CALL instruction; possible change to lesser privilege
• RTD Return and Deallocate; Motorola 680x0, Motorola 68300; fetches the return address from the top of the system stack, increments the system stack pointer by the specified displacement value (effectively deallocating temporary storage space from the stack), and changes program flow to the return address
• RTE Return from Exception; Motorola 680x0, Motorola 68300; transfers the value at the top of the system stack into the status register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer by a displacement value designated by format mode (effectively deallocating temporary storage space from the stack, the amount of space varying by type of exception that occurred), and changes program flow to the return address; privileged instruction (supervisor state)
• MOVEM Move Multiple; Motorola 680x0, Motorola 68300; move contents of a list of registers to memory or restore from memory to a list of registers
• LM Load Multiple; IBM 360/370; RS format; moves a series of full words (32 bits) of data from memory to a series of general purpose registers; main storage to register only; does not affect condition code
• STM STore Multiple; IBM 360/370; RS format; moves contents of a series of general purpose registers to a series of full words (32 bits) in memory; register to main storage only; does not affect condition code
• PUSHA Push All Registers; Intel 80x86; move contents all 16-bit general purpose registers to memory pointed to by stack pointer (in the order AX, CX, DX, BX, original SP, BP, SI, and DI ); does not affect flags
• PUSHAD Push All Registers; Intel 80386; move contents all 32-bit general purpose registers to memory pointed to by stack pointer (in the order EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI ); does not affect flags
• POPA Pop All Registers; Intel 80x86; move memory pointed to by stack pointer to all 16-bit general purpose registers (except for SP); does not affect flags
• POPAD Pop All Registers; Intel 80386; move memory pointed to by stack pointer to all 32-bit general purpose registers (except for ESP); does not affect flags
• STJ Store jump-register; MIX; move word or partial word field of data; jump register to main storage only
• NOP No Operation; Motorola 680x0, Motorola 68300; no change in processor state other than an advance of the program counter
• NOP No Operation; MIX; no change in processor state other than an advance of the program counter
• STOP Stop; Motorola 680x0, Motorola 68300; loads an immediate operand into the program status register (both user and supervisor portions), advances program counter to next instruction, and stops the processor from fetching and executing instructions; privileged instruction (supervisor state)
• HLT Halt; MIX; stop machine, computer restarts on next instruction
• LPSTOP Low Power Stop; Motorola 68300; loads an immediate operand into the program status register (both user and supervisor portions), advances program counter to next instruction, and stops the processor from fetchhing and executing instructions, the new interrupt mask is copied to the external bus interface (EBI), internal clocks are stopped, the processor remains stopped until a trace, higher interrupt than new mask, or reset exception occurs; privileged instruction (supervisor state)

condition codes

Condition codes are the list of possible conditions that can be tested during conditional instructions. Typical conditional instructions include: conditional branches, conditional jumps, and conditional subroutine calls. Some processors have a few additional data related conditional instructions, and some processors make every instruction conditional. Not all condition codes available for a processor will be implemented for every conditional instruction.

Zero is mathematically neither positive nor negative, but for processor condition codes, most processors treat zero as either a positive or a negative numbers. Processors that treat zero as a positive number include the Motorola 680x0 and Motorola 68300.

• A above; Intel 80x86; unsigned conditional transfer; equivalent to NBE; (not carry flag and not zero flag)
• AE above or equal; Intel 80x86; unsigned conditional transfer; equivalent to NB; (not carry flag
• B below; Intel 80x86; unsigned conditional transfer; equivalent to NAE; (carry flag)
• BE below or equal; Intel 80x86; unsigned conditional transfer; equivalent to NA; (carry flag or zero flag)
• C carry; Intel 80x86; unsigned conditional transfer; (carry flag)
• CC Carry Clear; Motorola 680x0, Motorola 68300; not carry flag
• CS Carry Set; Motorola 680x0, Motorola 68300; carry flag
• E equal; Intel 80x86; unsigned conditional transfer; equivalent to Z; (zero flag)
• EQ Equal; Motorola 680x0, Motorola 68300; zero flag
• F False (never true); Motorola 680x0, Motorola 68300; never
• G greater; Intel 80x86; signed conditional transfer; equivalent to NLE; (not ((sign flag xor overflow flag) or zero flag))
• GE Greater or Equal; Motorola 680x0, Motorola 68300; (negative flag and overflow flag) or (not negative flag and not overflow flag)
• GE greater or equal; Intel 80x86; signed conditional transfer; equivalent to NL; (not (sign flag xor overflow flag))
• GT Greater Than; Motorola 680x0, Motorola 68300; (negative flag and overflow flag and not zero flag) or (not negative flag and not overflow flag and not zero flag)
• HI High; Motorola 680x0, Motorola 68300; not carry flag and not zero flag
• L less; Intel 80x86; signed conditional transfer; equivalent to NGE; (sign flag xor overflow flag)
• LE Less or Equal; Motorola 680x0, Motorola 68300; (zero flag) or (negative flag and not overflow flag) or (not negative flag and overflow flag)
• LE less or equal; Intel 80x86; signed conditional transfer; equivalent to NG; ((sign flag xor overflow flag) or zero flag)
• LS Low or Same; Motorola 680x0, Motorola 68300; carry flag or zero flag
• LT Less Than; Motorola 680x0, Motorola 68300; (negative flag and not overflow flag) or (not negative flag and overflow flag)
• MI Minus; Motorola 680x0, Motorola 68300; negative flag
• NA not above; Intel 80x86; unsigned conditional transfer; equivalent to BE; (carry flag or zero flag)
• NAE not above nor equal; Intel 80x86; unsigned conditional transfer; equivalent to B; (carry flag)
• NB not below; Intel 80x86; unsigned conditional transfer; equivalent to AE; (not carry flag)
• NBE not below nor equal; Intel 80x86; unsigned conditional transfer; equivalent to A; (not carry flag and not zero flag)
• NC not carry; Intel 80x86; unsigned conditional transfer; (not carry flag)
• NE Not Equal; Motorola 680x0, Motorola 68300; not zero flag
• NE not equal; Intel 80x86; unsigned conditional transfer; equivalent to NZ; (not zero flag)
• NG not greater; Intel 80x86; signed conditional transfer; equivalent to LE; ((sign flag xor overflow flag) or zero flag)
• NGE not greater nor equal; Intel 80x86; signed conditional transfer; equivalent to L; (sign flag xor overflow flag)
• NL not less; Intel 80x86; signed conditional transfer; equivalent to GE; (not (sign flag xor overflow flag))
• NLE not less nor equal; Intel 80x86; signed conditional transfer; equivalent to G; (not ((sign flag xor overflow flag) or zero flag))
• NO not overflow; Intel 80x86; signed conditional transfer; (not overflow flag)
• NP not parity; Intel 80x86; unsigned conditional transfer; equivalent to PO; (not parity flag)
• NS not sign (positive or zero); Intel 80x86; signed conditional transfer; (not sign flag)
• NZ not zero; Intel 80x86; unsigned conditional transfer; equivalent to NE; (not zero flag)
• O overflow; Intel 80x86; signed conditional transfer; (overflow flag)
• P parity; Intel 80x86; unsigned conditional transfer; equivalent to PE; (parity flag)
• PE parity; Intel 80x86; unsigned conditional transfer; equivalent to P; (parity flag)
• PL Plus; Motorola 680x0, Motorola 68300; not negative flag
• PO parity odd; Intel 80x86; unsigned conditional transfer; equivalent to NP; (not parity flag)
• S sign (negative); Intel 80x86; signed conditional transfer; (sign flag)
• T True (always true); Motorola 680x0, Motorola 68300; always
• VC Overflow Clear; Motorola 680x0, Motorola 68300; not overflow flag
• VS Overflow Set; Motorola 680x0, Motorola 68300; overflow flag
• Z zero; Intel 80x86; unsigned conditional transfer; equivalent to E; (zero flag)

Digital Equipment Corporation’s “VAX Architecture Reference Manual” gives the following example of the CASE instruction using the VAX PASCAL compiler (quoted under the fair use doctrine):

casel i, #32,
1$: .word sin - 1$ ; Selector is 32.
.word cos - 1$ ; Selector is 33.
.word exp - 1$ ; Selector is 34.
.word ln - 1$ ; Selector is 35.
.word arctanh - 1$ ; Selector is 36.
.word arctanh - 1$ ; Selector is 37.
otherwise:
movl reserved, x ; Selector is less than.
; 32 or greater than 37

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